FPGA Hardware Engineer Resume - Thomas Anderson

Professional resume for FPGA Hardware Engineer with digital design expertise.

Thomas Anderson

+1 (555) 012-3456 thomas.anderson@email.com 8years Birth Date: 1991-05-10 male

Job Intention

Desired Position	FPGA Hardware Engineer
Expected Salary	$145,000 - $180,000
City	Santa Clara, CA

Self Evaluation

Experienced FPGA engineer with 8 years of expertise in RTL design, verification, and implementation. Proficient in Verilog, SystemVerilog, and VHDL. Successfully delivered 15+ FPGA projects for aerospace, automotive, and data center applications. Expert in Xilinx and Intel FPGA architectures.

Work Experience

Aerospace Defense Corp.

2020-07

Department: Hardware Engineering

Senior FPGA Engineer

Lead FPGA development for satellite communication systems using Xilinx UltraScale+. Implemented high-speed SerDes interfaces at 28Gbps. Achieved DO-254 DAL-A certification for safety-critical avionics. Reduced power consumption by 45% through clock gating and resource optimization.

Automotive Electronics Inc.

2017-08 - 2020-06

Department: R&D

FPGA Design Engineer

Developed ADAS processing pipeline on Intel Stratix FPGAs. Integrated camera sensors and LiDAR processing achieving real-time object detection. Performed timing closure and static timing analysis meeting ISO 26262 ASIL-D requirements.

Semiconductor Solutions

2015-06 - 2017-07

Department: Digital Design

Junior FPGA Engineer

Designed digital signal processing blocks for software-defined radio. Verified designs using SystemVerilog and UVM. Supported board bring-up and hardware debugging.

Project Experience

Ultra-Low-Latency Trading Accelerator

2023-02 - 2023-10

Lead FPGA Engineer

Architected low-latency trading accelerator FPGA for high-frequency trading platform.

Responsibility Architecture design, RTL implementation, timing closure, hardware/software co-design.

Achievement Achieved 10Tbps throughput. Reduced latency to <1μs.

Industrial Motor Control FPGA

2022-05 - 2022-12

Senior FPGA Engineer

Designed motor control FPGA for industrial automation with field-oriented control.

Responsibility PWM generation, encoder interfaces, EtherCAT communication, safety monitoring.

Achievement Passed all EMI/EMC tests on first attempt. Shipped 10K+ units.

Education

Georgia Institute of Technology

2013-09 - 2015-05

Master of Science , Electrical Engineering

GPA: 3.85/4.0. Digital Systems Specialization.

University of California, Berkeley

2009-09 - 2013-05

Bachelor of Science , Electronics Engineering

GPA: 3.75/4.0.

Skills

RTL Design (Verilog, SystemVerilog, VHDL) Xilinx (Virtex, Kintex, Zynq) Intel/Altera (Stratix, Arria) High-Speed Interfaces (PCIe, DDR, JESD204B) Verification (UVM, ModelSim, VCS) DSP/Signal Processing

Certificates

2023-05

Xilinx certification

2022-09

Functional safety certification

Highlights

ATS-friendly layout to pass screening
Polished design that stands out
Fully editable content with AI writing help
One-click PDF export, ready to apply
Shareable link for online applications

Template Info

RegionUS

Categoryinternet

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