Semiconductor Process Engineer Resume - Dr. Wei Zhang

Professional resume for Semiconductor Process Engineer with advanced node expertise.

Dr. Wei Zhang

+1 (555) 567-8901 wei.zhang@email.com 8years Birth Date: 1989-12-03 male

Job Intention

Desired Position	Semiconductor Process Engineer
Expected Salary	$140,000 - $180,000
City	San Jose, CA

Self Evaluation

Experienced process engineer with 8 years developing advanced semiconductor manufacturing processes at leading foundries. Expert in lithography, etch, and thin film processes for sub-7nm nodes. Improved yield by 15% through DOE optimization and defect reduction. Published 12 peer-reviewed papers and hold 5 patents. Strong statistical analysis skills with JMP and Minitab.

Work Experience

Leading Semiconductor Foundry

2020-08

Department: Technology Development

Senior Process Engineer

Develop and optimize lithography processes for 5nm and 3nm technology nodes. Lead cross-functional teams resolving yield excursions and defect issues. Design experiments improving CD uniformity by 20%. Support high-volume manufacturing transfer achieving 95% on-time delivery. Mentor junior engineers on SPC and FMEA methodologies.

Chip Manufacturer

2017-06 - 2020-07

Department: Manufacturing

Process Engineer

Owned etch process module for 14nm logic production. Monitored process stability using SPC charts maintaining Cpk >1.67. Led continuous improvement projects reducing particle defects by 40%. Supported equipment installation and qualification for new tool purchases.

Semiconductor Company

2016-06 - 2017-05

Department: R&D

Process Integration Intern

Characterized novel transistor architectures for sub-10nm nodes. Performed TCAD simulations optimizing device performance. Analyzed electrical data correlating process parameters to device metrics.

Project Experience

5nm HPC Yield Ramp Program

2023-01 - 2023-09

Process Lead

Led comprehensive yield enhancement program for 5nm high-performance computing product.

Responsibility Root cause analysis, DOE execution, excursion prevention, yield modeling, cross-functional coordination.

Achievement Achieved 15% yield improvement. Generated $50M annual savings.

Fab Cycle Time Reduction Initiative

2022-04 - 2022-11

Technical Lead

Optimized process flow eliminating bottlenecks and non-value-added steps.

Responsibility Value stream mapping, bottleneck analysis, process simplification, automation implementation.

Achievement Reduced cycle time by 25%. Increased fab output by 10K wafers/month.

Education

Stanford University

2012-09 - 2017-05

Doctor of Philosophy , Electrical Engineering

GPA: 3.9/4.0. Semiconductor Devices Focus.

UC Berkeley

2008-09 - 2012-05

Bachelor of Science , Physics

GPA: 3.9/4.0. Summa Cum Laude.

Skills

Semiconductor Fabrication Processes Lithography & Etch Design of Experiments (DOE) Statistical Process Control (SPC) Yield Enhancement & Defect Analysis JMP/Minitab Data Analysis

Certificates

2023-05

Six Sigma certification

2021-08

Process engineering certification

Highlights

ATS-friendly layout to pass screening
Polished design that stands out
Fully editable content with AI writing help
One-click PDF export, ready to apply
Shareable link for online applications

Template Info

RegionUS

Categoryhardware

Export formatPDF / Link

Like this template?

Free to use — build a pro resume in 5 minutes

Three Steps to a Pro Resume

A simple flow so you can focus on your content

Pick a template

Choose from curated templates that fit your role and open the editor in one click.